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Ordering number : ENA1335
LC87F2708A
Overview
CMOS IC FROM 8K byte, RAM 512 byte on-chip
8-bit 1-chip Microcontroller
The LC87F2708A is an 8-bit microcotroller that, centered around a CPU running at a minimum bus cycle time of 100ns, integrates on a single chip a number of hardware features such as 8K-byte flash ROM (onboard programmable), 512-byte RAM, an on-chip debugger, a sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers or PWMs), a synchronous SIO interface, a high-speed 12-bit PWM, two high-speed pulse width/period counters, a 7-channel AD converter with 12-/8-bit resolution selector, an analog comparator, a watchdog timer, an internal reset circuit, a system clock frequency divider, and a 16-source 10-vector interrupt feature.
Features
Flash ROM * Capable of on-board programming of voltage source (3.0 to 5.5V) * Block-erasable in 128 byte units * 8192 x 8 bits RAM * 512 x 9 bits
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
Ver.0.12
O2908HKIM 20081022-S00006 No.A1335-1/21
LC87F2708A
Minimum Bus Cycle Time Note1 * 100ns (10MHz) VDD=2.7 to 5.5V Note2 Minimum Instruction Cycle Time * 300ns (10MHz) VDD=2.7 to 5.5V Note2 Note1: The bus cycle time here refers to the ROM read speed. Note2: Use this product in a voltage range of 3.0 to 5.5V because the minimum release voltage (PORRL) of the power-on reset (POR) circuit is 2.87V0.12V. Ports * I/O ports Ports whose I/O direction can be designated in 1-bit units 11 (P10 to P16, P30 to P33) * Reset pins 1 (RES) * Power pins 2 (VSS1, VDD1) Timers * Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) x 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) * Timer 1: 16-bit timer/counter that can provide with PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/ counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler x 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle output also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (Lower-order 8 bits may be used as PWM) Serial Interface * SIO7: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3 tCYC) High-Speed 12-bit PWM * System clock/high-speed RC oscillation clock (20MHz or 40MHz) operation selectable * Duty/period programmable * Continuous PWM output/specific count PWM output (automatic stop) selectable High-speed Pulse/Period Counter * HCT1: High-speed RC pulse width/period counter 1 1) System clock/high-speed RC oscillation clock (20MHz or 40MHz) operation selectable 2) H-level width/L-level width/period measurement modes selectable 3) Input triggering noise filter * HCT2: High-speed pulse width/period counter 2 1) System clock/high-speed RC oscillation clock (20MHz or 40MHz) operation selectable 2) Can measure both L-level width and period simultaneously. 3) Input triggering noise filter 4) Input trigger selectable (from 3 signals, i.e., P11/HCT2IN, P31/HCT2IN, and analog comparator output) AD Converter: 12 bits x 7 channels * 12-/8-bits AD converter resolution selectable Analog Comparator * Sends output to the P32/CMPO port (polarity selectable). * Edge detection function (shared with INTC and also allows the selection of the noise filter function)
No.A1335-2/21
LC87F2708A
Watchdog Timer * Can generate the internal reset signal on a timer overflow monitored by the WDT-dedicated low-speed RC oscillation clock (30kHz). * Allows selection of continue, stop, or hold mode operation of the counter on entry into the HALT/ HOLD mode. Interrupts Source Flags * 16 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence.
No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INTA INTB INTC/T0L/INTE INTD/INTF T0H/SIO7 T1L/T1H HCT1 HCT2 ADC/HPWM automatic stop/HPWM cycle None Interrupt Source
* Priority levels X > H > L * Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 256levels maximum (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions * 16 bits x 8 bits (5 tCYC execution time) * 24 bits x 16 bits (12 tCYC execution time) * 16 bits / 8 bits (8 tCYC execution time) * 24 bits / 16 bits (12 tCYC execution time) Oscillation Circuits * Medium speed RC oscillation circuit (internal): For system clock (1MHz) * Low speed RC oscillation circuit (internal): For watchdog timer (30kHz) * High speed RC oscillation circuit (internal): For system clock (20MHz or 40MHz) 1) 2 source oscillation frequencies (20MHz or 40MHz) selectable for the high-speed RC oscillation circuit by optional configuration. System Clock Divider Function * Can run on low current. * The minimum instruction cycle selectable from 300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, and 76.8s (when high speed RC oscillation is selected for system clock.). Internal reset circuit * Power-on reset (POR) function 1) POR reset is generated only at power-on time. 2) The POR release level can be selected from 3 levels (2.87V, 3.86V, and 4.35V) by optional configuration. * Low-voltage detection reset (LVD) function 1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) The use or disuse of the LVD function and the low voltage threshold level (3 levels: 2.81V, 3.79V and 4.28V). can be selected by optional configuration.
No.A1335-3/21
LC87F2708A
Standby Function * HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) There are the following three ways of resetting the HALT mode. (1) Setting the reset pin to the low level (2) Generating a reset signal via the watchdog timer or brown-out detector (3) Having an interrupt generated * HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The medium- and high-speed RC oscillation circuits automatically stop operation. 2) There are the following four ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) Generating a reset signal via the watchdog timer or brown-out detector (3) Setting at least one of the INTA, INTB, INTC, INTD, INTE, and INTF pins to the specified level (4) Applying input signals to the IN+ and IN- pins so that the analog comparator output is set to the specified level (when the analog comparator output is assigned to the INTC input) On-chip Debugger Function * Supports software debugging with the IC mounted on the target board. * 3 channels of on-chip debugger pins are available. Data Security Function Note3 * Protects the program data stored in flash memory from unauthorized read or copy. Note3: This data security function does not necessarily provide absolute data security. Package Form * MFP14S(225mil): Lead-free Type Development Tools * On-chip debugger: TCB87 Type B + LC87F2708A Flash ROM Programming Board
Maker Model SKK-DBG Type B (SANYO FWS) Version
Note4
Device
Application Version SANYO 1.04 or later Chip Data Version 2.10 or later LC87F2708A
Note4: Check for the latest version.
No.A1335-4/21
LC87F2708A
Package Dimensions
unit : mm (typ) 3111A
8.0 14 8
4.4 6.4
(1.0)
1.0
0.35
SANYO : MFP14S(225mil)
Pin Assignment
P31/INTB/HCT2IN/DBGP01
0.1 (1.5)
1.7MAX
1
7
0.15
0.63
1
14
VDD1
P30/INTA/HCT1IN/DBGPX0
2
13
P32/INTC/CMPO/DBGP11
RES
3
12
P33/INTD/HPWM/DBGP12
P10/SO7/INTE/AN0/DBGP02
4
LC87F2708A
11
P11/SI7/SB7/INTE/IN0+/HCT2IN/AN1
VSS1
5
10
P12/SCK7/INTF/IN0-/AN2
P16/INTF/IN1-/AN6
6
9
P13/INTF/T1PWML/AN3/DBGP20
P15/INTE/IN1+/AN5/DBGP22
7
8
P14/INTE/T1PWMH/AN4/DBGP21 Top view
SANYO: MFP14S(225mil) "Lead-free Type"
MFP14S 1 2 3 4 5 6 7
NAME P31/INTB/HCT2IN/DBGP01 P30/INTA/HCT1IN/DBGPX0 RES P10/SO7/INTE/AN0/DBGP02 VSS1 P16/INTF/IN1-/AN6 P15/INTE/IN1+/AN5/DBGP22
MFP14S 8 9 10 11 12 13 14
NAME P14/INTE/T1PWMH/AN4/DBGP21 P13/INTF/T1PWML/AN3/DBGP20 P12/SCK7/INTF/IN0-/AN2 P11/SI7/SB7/INTE/IN0+/HCT2IN/AN1 P33/INTD/HPWM/DBGP12 P32/INTC/CMPO/DBGP11 VDD1
No.A1335-5/21
LC87F2708A
System Block Diagram
Interrupt control
IR
PLA
Standby control
Flash ROM
High-speed Freq. Divider RC Clock Mediumgenerator speed RC
PC
RES WDT (Low-speed RC) Reset circuit (LVD/POR) DATA BUS Reset control ACC
B register
C register
SIO7
Bus interface
Timer 0
Port 1 (INTE to INTF) Port 3 (INTA to INTD) PSW ADC RAR
ALU
Timer 1 DATA BUS
High-speed PWM
High-speed pulse width/period counter1
High-speed pulse width/period counter2 RAM
Analog comparator Stack pointer
On-chip debugger
No.A1335-6/21
LC87F2708A
Pin Description
Pin Name VSS1 VDD1 PORT1 P10 to P16 I/O I/O - power supply pin + power supply pin * 7-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units * Multiplexed pins P10: SIO7 data output P11: SIO7 data input/bus I/O/high-speed pulse width/period counter 2 input P12: SIO7 clock I/O P13: Timer 1 PWML output P14: Timer 1 PWMH output P10, P11, P14, P15: INTE input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H capture input P12, P13, P16: INTF input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H capture input AD converter input port: AN0 to AN6(P10 to P16) Analog comparator input port 0: IN0+, IN0-(P11, P12) Analog comparator input port 1: IN1+, IN1-(P15, P16) On-chip debugger pin 1: DBGP02 (P10) On-chip debugger pin 3: DBGP20 to DBGP22 (P13 to P15) * Interrupt acknowledge type Rising INTE INTF PORT3 P30 to P33 I/O * 4-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units * Multiplexed pins P30: INTA input/HOLD release input/timer 0L capture input/high-speed pulse width/ period counter 1 input P31: INTB input/HOLD release input/timer 0H capture input/high-speed pulse width/ period counter 2 input P32: INTC input/HOLD release input/timer 0 event input/timer 0L capture input/ analog comparator output P33: INTD input/HOLD release input/timer 0 event input/timer 0H capture input/ high-speed PWM output On-chip debugger pin 1: DBGPX0 to DBGP01 (P30 to P31) On-chip debugger pin 2: DBGPX0 to DBGP12 (P30, P32 to P33) * Interrupt acknowledge type Rising INTA INTB INTC INTD RES I/O enable enable enable enable Falling enable enable enable enable Rising & Falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable No enable enable Falling enable enable Rising & Falling enable enable H level disable disable L level disable disable Yes Description Option No No Yes
External reset input/internal reset output
No.A1335-7/21
LC87F2708A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode.
Port Name P10 to P16 Option Sselected in Units of 1 bit Option Type 1 2 P30 to P33 1 bit 1 2 CMOS Nch-open drain CMOS Nch-open drain Output Type Pull-up Resistor Programmable Programmable Programmable Programmable
On-chip Debugger Pin Processing
For the processing of the on-chip debugger pins, refer to the separately available documents entitled "RD87 On-chip Debugger Installation" and "LC872000 Series On-chip Debugger Pin Processing."
User Option Table
Option Name Port output type Option Type P10 to P16 Flash Version Option Switched in Unit of 1 bit CMOS Nch-open drain P30 to P33 1 bit CMOS Nch-open drain Program start address Brown-out detector reset function Brown-out detector function Brown-out trip level Power-on-reset function High-speed RC oscillator circuit Oscillation frequency Power-on-reset level 00000h 01E00h Enable: Used Disable: Not Used 3 levels 3 levels 20 MHz 40 MHz Description
No.A1335-8/21
LC87F2708A
Absolute Maximum Ratings at Ta = 25C, VSS1 =0V
Parameter Maximum supply voltage Input voltage Input/output voltage Peak output current IOPH(2) High level output current Mean output current (Note 1-1) Total output current IOAH(2) IOAH(3) Peak output current Low level output current Mean output current (Note 1-1) Total output current IOAL(2) IOAL(3) Power dissipation Pd max(1) Pd max(2) IOAL(1) * Port 10 * Ports 30, 31 * Ports 11 to 16 * Ports 32, 33 * Port 1 * Port 3 MFP14S(225mil) Total of currents at all applicable pins Total of currents at all applicable pins Total of currents at all applicable pins * Ta=-40C to +85C * Independent package * Ta=-40C to +85C * Mounted on thermal test board * (Note 1-2) Operating ambient temperature Storage ambient temperature Tstg Topr -40 -55 +85 C +125 260 IOPL(1) IOPL(2) IOML(1) IOML(2) IOMH(2) IOAH(1) Port 3 * Ports 10, 15, 16 * Ports 30, 31 * Ports 11 to 14 * Ports 32, 33 * Port 1 * Port 3 Port 1 Port 3 Port 1 Port 3 IOMH(1) Port 3 Port 1 IOPH(1) VI VIO RES * Port 1 * Port 3 Port 1 CMOS output selected per applicable pin CMOS output selected per applicable pin CMOS output selected per applicable pin CMOS output selected per applicable pin Total of currents at all applicable pins Total of currents at all applicable pins Total of currents at all applicable pins Per applicable pin Per applicable pin Per applicable pin Per applicable pin Symbol VDD max Pin/Remarks VDD1 Conditions VDD[V] min -0.3 -0.3 -0.3 -7.5 -10 -5 -7.5 -20 -20 -35 15 10 10 7.5 25 35 55 113 mW mA Specification typ max +6.5 VDD+0.3 VDD+0.3 V unit
Note 1-1: The mean output current is a mean value measured over 100ms. Note 1-2: Thermal test board used conforms to SEMI (size: 76.1x114.3x1.6tmm, glass epoxy board).
No.A1335-9/21
LC87F2708A
Allowable Operating Range at Ta = -40C to +85C, VSS1 = 0V
Parameter Operating supply voltage (Note 2-1) Memory sustaining supply voltage High level input voltage VIH(2) Low level input voltage VIL(1) VIH(1) * Port 1 * Port 3 RES * Port 1 * Port 3 Output disabled Output disabled 2.7 to 5.5 2.7 to 5.5 4.0 to 5.5 2.7 to 4.0 VIL(2) Instruction cycle time (Note 2-2) Oscillation frequency range FmHRC(2) FmHRC(3) FmHRC(4) FmHRC(5) FmHRC(1) * High-speed RC oscillation * 40MHz selected as option * Ta=-20C to +85C * High-speed RC oscillation * 40MHz selected as option * Ta=-40C to +85C * High-speed RC oscillation * 20MHz selected as option * Ta=-20C to +85C FmHRC(6) * High-speed RC oscillation * 20MHz selected as option * Ta=-40C to +85C FmRC FmSLRC Oscillation stabilization time tmsHRC Medium-speed RC oscillation Low-speed RC oscillation * When high-speed RC oscillation state is switched from stopped to enabled. * See Fig. 2. 2.7 to 5.5 100 s 2.7 to 5.5 2.7 to 5.5 0.5 15 1.0 30 2.0 60 kHz 2.7 to 5.5 18.7 20 21.3 3.0 to 5.5 19 20 21 4.5 to 5.5 3.5 to 5.5 2.7 to 5.5 37.6 36.8 32 40 40 40 42.4 43.2 43.2 MHz 4.5 to 5.5 38 40 42 tCYC 2.7 to 5.5 0.272 100 s RES 2.7 to 5.5 0.3VDD +0.7 0.75VDD VSS VSS VSS VDD VDD 0.1VDD +0.4 0.2VDD 0.25VDD V VHD VDD1 RAM and register contents sustained in HOLD mode 2.0 5.5 Symbol VDD Pin/Remarks VDD1 Conditions VDD[V] 0.272s tCYC 100s 2.7 5.5 min Specification typ max unit
Note 2-1: Use this product in a voltage range of 3.0 to 5.5V because the minimum release voltage (PORRL) of the power-on reset (POR) circuit is 2.87V0.12V. Note 2-2: Relationship between tCYC and oscillation frequency is as follows: * When system clock source is set to medium-speed RC oscillation 3/FmRC at a division ratio of 1/1, 6/FmRC at a division ratio of 1/2, 12/FmRC a division ratio of 1/4, and so forth * When system clock source is set to high-speed RC oscillation (40MHz selected by optional configuration) 12/FmHRC at a division ratio of 1/1, 24/FmHRC at a division ratio of 1/2, 48/FmHRC a division ratio of 1/4, and so forth * When system clock source is set to high-speed RC oscillation (20MHz selected by optional configuration) 6/FmHRC at a division ratio of 1/1, 12/FmHRC at a division ratio of 1/2, 24/FmHRC a division ratio of 1/4, and so forth
No.A1335-10/21
LC87F2708A
Electrical Characteristics at Ta = -40C to +85C, VSS1 = 0V
Parameter High level input current Symbol IIH(1) Pin/Remarks * Port 1 * Port 3 Conditions VDD[V] * Output disabled * Pull-up resistor off * VIN=VDD (including output Tr. off leakage current) IIH(2) Low level input current IIL RES * Port 1 * Port 3 VIN=VDD * Output disabled * Pull-up resistor off * VIN=VSS (including output Tr. off leakage current) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) Pull-up resistance Rpu(1) Rpu(2) Rpu(3) Hysteresis voltage VHYS * Port 1 * Port 3 RES * Port 1 * Port 3 * RES Pin capacitance CP All pins * VIN=VSS for pins other than that under test * f=1MHz * Ta=25C 2.7 to 5.5 10 pF 2.7 to 5.5 0.1VDD V Port 3 CMOS output type port 1 CMOS output type port 3 Port 1 IOH=-1mA IOH=-0.35mA IOH=-5mA IOH=-0.7mA IOL=10mA IOL=1.4mA IOL=5mA IOL=0.7mA VOH=0.9VDD 4.5 to 5.5 2.7 to 5.5 4.5 to 5.5 2.7 to 5.5 4.5 to 5.5 2.7 to 5.5 4.5 to 5.5 2.7 to 5.5 4.5 to 5.5 2.7 to 4.5 2.7 to 5.5 15 18 216 35 50 360 VDD-1 VDD-0.4 VDD-1.5 VDD-0.4 1.5 0.4 1.5 0.4 80 150 504 k V 2.7 to 5.5 -1 2.7 to 5.5 1 A 2.7 to 5.5 1 min Specification typ max unit
No.A1335-11/21
LC87F2708A
Serial I/O Characteristics at Ta = -40C to +85C, VSS1 = 0V
1. SIO7 Serial I/O Characteristics (Note 4-1-1)
Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(1) SB7(P11), SI7(P11) Data hold time thDI(1) 0.03 Output delay Input clock time tdDO(1) SO7(P10), SB7(P11) * Must be specified with respect to rising edge of SIOCLK. * Must be specified as the time to the beginning of output state change in open drain output Output clock tdDO(2) mode * See Fig. 4. 2.7 to 5.5 (1/3)tCYC +0.05 1tCYC +0.05 s * Must be specified with respect to rising edge of SIOCLK. * See Fig. 4. 2.7 to 5.5 0.03 tSCKH(2) tSCK(2) tSCKL(2) SCK7(P12) * CMOS output selected * See Fig. 4. 2.7 to 5.5 tSCKH(1) Symbol tSCK(1) tSCKL(1) Pin/ Remarks SCK7(P12) Conditions VDD[V] * See Fig. 4 (Note 4-1-2) 2.7 to 5.5 min 2 1 tCYC 1 4/3 1/2 tSCK 1/2 Specification typ max unit
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in transmission/reception mode, the time from SI7RUN being set when serial clock is "H" to the first falling edge of the serial clock must be longer than 1tCYC.
Serial output
Serial clock
No.A1335-12/21
LC87F2708A
Pulse Input Conditions at Ta = -40C to +85C, VSS1 = 0V
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pin/Remarks INTA(P30), INTB(P31), INTD(P33), INTE (P10, P11, P14, P15), INTF(P12, P13, P16) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIH(5) tPIL(5) tPIH(6) tPIL(6) tPIH(7) tPIL(7) tPIL(8) RES HCT2IN(P11, P31) INTC(P32) when noise filter time constant is "none" INTC(P32) when noise filter time constant is "1/16" INTC(P32) when noise filter time constant is "1/32" INTC(P32) when noise filter time constant is "1/64" HCT1IN(P30) * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. Pulses can be recognized as signals by the high-speed pulse width/period counter 1. Pulses can be recognized as signals by the high-speed pulse width/period counter 2. Resetting is enabled. 2.7 to 5.5 200 2.7 to 5.5 6 2.7 to 5.5 3 H1CK (Note 5-1) H2CK (Note 5-2) s 2.7 to 5.5 256 2.7 to 5.5 128 2.7 to 5.5 64 2.7 to 5.5 1 tCYC Conditions VDD[V] * Interrupt source flag can be set. * Event inputs for timers 0 and 1 are enabled. 2.7 to 5.5 1 min. Specification typ. max. unit
Note 5-1: H1CK denotes the period of the base clock (1 to 8 x high-speed RC oscillation clock or system clock) for the high-speed pulse width/period counter 1. Note 5-2: H2CK denotes the period of the base clock (2 to 16 x high-speed RC oscillation clock or system clock) for the high-speed pulse width/period counter 2.
Comparator Characteristics at Ta=-40C to +85C, VSS1 = 0V
Parameter Common mode input voltage range Offset voltage Response time VOFF tRT Symbol VCMIN Pin/Remarks IN0+(P11), IN0-(P12), IN1+(P15), IN1-(P16) Within common mode input voltage range * Within common mode input voltage range * Input amplitude=100mV * Overdrive=50mV Operation stabilization time (Note 6-1) tCMW 2.7 to 5.5 1.0 s 2.7 to 5.5 200 600 ns 2.7 to 5.5 10 2.7 to 5.5 VSS Conditions VDD[V] min Specification typ max VDD -1.5 30 unit
V
mV
Note 6-1: The interval after CMPON is set till the operation gets stabilized.
No.A1335-13/21
LC87F2708A
AD Converter Characteristics at VSS1 = 0V
<12-bits AD Converter Mode/Ta = -40C to +85C >
Parameter Resolution Absolute accuracy Conversion time tCAD * See Conversion time calculation Symbol N ET Pin/Remarks AN0(P10) to AN6(P16) (Note 7-1) Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 4.0 to 5.5 3.0 to 5.5 3.0 to 5.5 VAIN=VDD VAIN=VSS 3.0 to 5.5 3.0 to 5.5 -1 38 75.8 VSS min Specification typ 12 max unit bit
16
104.3 104.3 VDD 1
LSB
method
* (Note 7-2) Analog input voltage range Analog port input current IAINH IAINL VAIN
s
V A
<8-bits AD Converter Mode/Ta = -40C to +85C >
Parameter Resolution Absolute accuracy Conversion time tCAD * See Conversion time calculation Symbol N ET Pin/Remarks AN0(P10) to AN6(P16) (Note 7-1) Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 4.0 to 5.5 3.0 to 5.5 3.0 to 5.5 VAIN=VDD VAIN=VSS 3.0 to 5.5 3.0 to 5.5 -1 23.4 46.7 VSS min Specification typ 8 1.5 64.3 64.3 VDD 1 s max unit bit LSB
method.
* (Note 7-2) Analog input voltage range Analog port input current IAINH IAINL VAIN
V A
Conversion time calculation formulas: 12-bits AD Converter Mode: tCAD(Conversion time) = ((52/(AD division ratio))+2)x(1/3)xtCYC 8-bits AD Converter Mode: tCAD(Conversion time) = ((32/(AD division ratio))+2)x(1/3)xtCYC
High-speed RC oscillation (FmHRC) 40MHz/20MHz Supply voltage range (VDD) 4.0V to 5.5V 3.0V to 5.5V System clock division ratio (SYSDIV) 1/1 1/1 Cycle time (tCYC) 300ns 300ns AD division ratio (ADDIV) 1/8 1/16 12-bits AD 41.8s 83.4s Conversion time (tCAD) 8-bits AD 25.8s 51.4s
Note 7-1: The quantization error (1/2LSB) is excluded from the absolute accuracy. The absolute accuracy is measured when no change occurs in the I/O state of the pins that are adjacent to the analog input channel during AD conversion processing. Note 7-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time the complete digital conversion value against the analog input value is loaded in the result register. * The conversion time is 2 times the normal-time conversion time when: * The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. * The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode.
No.A1335-14/21
LC87F2708A
Power-on Reset (POR) Characteristics at Ta = -40C to +85C, VSS1 = 0V
Specification Parameter POR release voltage Symbol PORRL Pin/Remarks Conditions * Option selected * See Fig. 6. (Note 8-1) Detection voltage unknown state Power supply rise time PORIS POUKS * See Fig. 6 (Note 8-2) * Power startup time from VDD=0V to 2.8V. Option selected voltage 2.87V 3.86V 4.35V min 2.75 3.73 4.21 typ 2.87 3.86 4.35 0.7 max 2.99 3.99 4.49 0.95 100 ms V unit
Note 8-1: The POR release voltage can be selected from three levels when the low-voltage detection feature is deselected. Note 8-2: There is an unpredictable period before the power-on reset transistor starts to turn on.
Low Voltage Detection Reset (LVD) Characteristics at Ta = -40C to +85C, VSS1 = 0V
Specification Parameter LVD reset Voltage (Note 9-2) Symbol LVDET Pin/Remarks Conditions * Option selected. * See Fig. 7. (Note 9-1) (Note 9-3) LVD voltage hysteresis LVHYS Option selected voltage 2.81V 3.79V 4.28V 2.81V 3.79V 4.28V Detection voltage unknown state Minimum low voltage detection width (response sensitivity) tLVDW LVUKS * See Fig. 7. (Note 9-4) * LVDET-0.5V * See Fig. 8. 0.2 ms 0.7 0.95 V min 2.71 3.69 4.18 typ 2.81 3.79 4.28 60 65 65 mV max 2.91 3.89 4.38 V unit
Note 9-1: The LVD reset voltage can be selected from three levels when the low-voltage detection feature is selected. Note 9-2: The hysteresis voltage is not included in the LVD reset voltage value. Note 9-3: There are cases when the LVD reset voltage value is exceeded when a greater change in the output level or large current is applied to the port. Note 9-4: There is an unpredictable period before the low-voltage detection resetting transistor starts to run.
No.A1335-15/21
LC87F2708A
Consumption Current Characteristics at Ta = -40C to +85C, VSS1 = 0V
Parameter Normal mode consumption current (Note 10-1) IDDOP(2) Symbol IDDOP(1) Pin/ Remarks VDD1 Conditions VDD[V] * FmHRC=40MHz oscillation mode * System clock set to high-speed RC, 10MHz (1/4 of 40MHz) * Medium-speed RC oscillation stopped * System clock frequency division ratio set to 1/1 IDDOP(3) * FmHRC=20MHz oscillation mode * System clock set to high-speed RC, 10MHz (1/2 of 20MHz) IDDOP(4) * Medium-speed RC oscillation stopped * System clock frequency division ratio set to 1/1 * High-speed RC oscillation stopped * System clock set to medium-speed RC IDDOP(6) HALT mode consumption current (Note 10-1) IDDHALT(2) IDDHALT(1) oscillation mode * System clock frequency division ratio set to 1/2 HALT mode * FmHRC=40MHz oscillation mode * System clock set to high-speed RC, 10MHz (1/4 of 40MHz) * Medium-speed RC oscillation stopped * System clock frequency division ratio set to 1/1 IDDHALT(3) HALT mode * FmHRC=20MHz oscillation mode * System clock set to high-speed RC, IDDHALT(4) 10MHz (1/2 of 20MHz) * Medium-speed RC oscillation stopped * System clock frequency division ratio set to 1/1 IDDHALT(5) HALT mode * High-speed RC oscillation stopped IDDHALT(6) * System clock set to medium-speed RC oscillation mode * System clock frequency division ratio set to 1/2 HOLD mode consumption current (Note 10-1) IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) IDDHOLD(4) IDDHOLD(5) IDDHOLD(6) IDDHOLD(7) IDDHOLD(8) IDDHOLD(9) IDDHOLD(10) IDDHOLD(11) IDDHOLD(12) IDDHOLD(13) IDDHOLD(14) HOLD mode * Ta=-10C to +50C HOLD mode * Ta=-40C to +85C HOLD mode * LVD option selected * Ta=-10C to +50C HOLD mode * LVD option selected * Ta=-40C to +85C HOLD mode * Watchdog timer active * Ta=-10C to +50C HOLD mode * Watchdog timer active * Ta=-40C to +85C HOLD mode * Comparator active (IN+=VDD, IN-=VSS) 2.7 to 3.6 65 100 2.7 to 3.6 4.5 to 5.5 2.7 to 3.6 4.5 to 5.5 2.7 to 3.6 4.5 to 5.5 2.7 to 3.6 4.5 to 5.5 2.4 3.1 2.4 3.4 1.7 3.4 1.7 110 4.2 39 25 10 6.0 42 27 160 A 4.5 to 5.5 2.7 to 3.6 4.5 to 5.5 2.7 to 3.6 4.5 to 5.5 2.7 to 3.6 0.16 0.04 0.02 0.04 0.02 3.1 0.55 3.0 1.8 34 22 6.8 4.5 to 5.5 0.32 1.0 2.7 to 3.6 1.6 2.5 4.5 to 5.5 2.5 3.9 2.7 to 3.6 2.0 3.1 4.5 to 5.5 3.2 5.0 2.7 to 3.6 4.5 8.6 4.5 to 5.5 7.1 12.8 2.7 to 3.6 4.9 9.4 4.5 to 5.5 7.8 14 min Specification typ max unit
IDDOP(5)
4.5 to 5.5 2.7 to 3.6
0.60 0.38
1.9 1.3 mA
Note 10-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors.
No.A1335-16/21
LC87F2708A
F-ROM Programming Characteristics at Ta = +10C to +55C, VSS1 = 0V
Parameter Onboard programming current Programming time tFW(1) tFW(2) * Erase operation * Programming operation 3.0 to 5.5 20 40 30 60 ms s Symbol IDDFW Pin/Remarks VDD1 Conditions VDD[V] * Microcontroller consumption current is excluded. 3.0 to 5.5 5 10 mA min Specification typ max unit
Power Pin Treatment Recommendations (VDD1, VSS1)
Connect bypass capacitors that meet the following conditions between the VDD1 and VSS1 pins: * Connect among the VDD1 and VSS1 pins and bypass capacitors C1 and C2 with the shortest possible heavy lead wires, making sure that the impedances between the both pins and the bypass capacitors are as equal as possible (L1=L1', L2=L2'). * Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel. The capacitance of C2 should be approximately 0.1F.
L2 L1 VSS1 C1 C2
VDD1 L1' L2'
No.A1335-17/21
LC87F2708A
0.5VDD
Figure 1 AC Timing Measurement Point
Power Reset time RES
VDD Operating VDD lower 0V
Medium-speed RC oscillation tmsHRC High-speed RC oscillation
Operating mode
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD/HALT release signal
No HOLD release signal
HOLD release signal valid
HALT release signal valid
Medium-speed RC oscillation tmsHRC High-speed RC oscillation
State
HOLD
HALT
Instruction execution
HOLD Release Signal and Oscillation Stabilization Time Figure 2 Oscillation Stabilization Times
No.A1335-18/21
LC87F2708A
VDD
RRES
RES CRES
Note: The external peripheral circuit differs depending on the way in which the power-on reset and low-voltage detection reset functions are used. Refer to the Chapter, entitled "Reset Function", of the user's manual.
Figure 3 Sample Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKH
Figure 4 Serial I/O Waveforms
tPIL
tPIH
Figure 5 Pulse Input Timing Signal Waveform
No.A1335-19/21
LC87F2708A
POR release voltage (PORRL)
(a)
(b)
VDD
Reset period Reset unknown-state (POUKS) RES
100s or longer
Reset period
Figure 6 Example of POR Only (LVD Deselected) Mode Waveforms (at Reset Pin with RRES Pull-up Resistor Only) * The POR circuit generates a reset signal only when the power voltage is raised from the VSS level. * No stable reset signal is generated if power is turned on again when the power voltage does not go down to the VSS level as shown in (a). If this case is anticipated, use the LVD function as explained below or configure an external reset circuit. * A reset is effected only when power is turned on again after the power voltage goes down to and remains at the VSS level for 100s or longer as shown in (b).
LVD hysteresis width (LVHYS) LVD release voltage (LVDET+LVHYS)
VDD LVD voltage (LVDET) Reset period Reset unknown-state (LVUKS) RES Reset period Reset period
Figure 7 Example of POR + LVD Mode Waveforms (at Reset Pin with RRESS Pull-up Resistor Only) * A reset is effected both when power is turned on and when it goes down. * The hysteresis width (LVHYS) is introduced in the LVD circuit to prevent the iterations of the IC entering and exiting the reset state near the detection threshold level.
No.A1335-20/21
LC87F2708A
VDD
LVD release voltage
LVD voltage
tLVDW
LVDET-0.5V
VSS
Figure 8 Minimum Low Voltage Detection Width (Example of Short Interruption of Power/Power Fluctuation Waveform)
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of October, 2008. Specifications and information herein are subject to change without notice.
PS No.A1335-21/21

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